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MTB10N60E7
Advance Information
Preferred Device
TMOS 7 E-FETTM High Energy Power FET
N-Channel Enhancement-Mode Silicon Gate
The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
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TMOS POWER FET 10 AMPERES 600 VOLTS RDS(on) = 0.75
N-Channel D
* Ultra Low On-Resistance Provides Higher Efficiency * Reduced Gate Charge
Features Common to TMOS 7 and TMOS E-FETS
(R)
G S
* * * * *
Avalanche Energy Specified Diode Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Industry Standard D2PAK Surface Mount Package Surface Mount Package Available in 24 mm, 13-inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
1 Unit Vdc Vdc Vdc 2 3 D2PAK CASE 418B STYLE 2 Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage -- Continuous -- Non-Repetitive (tp Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS 400 RJC RJA RJA TL 0.62 62.5 50 260 C/W MTB10N60E7 C MTB10N60E7T4 Value 600 600
4
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
v10 ms)
"20 "30
10 8.0 35 201 1.61 - 55 to 150
Drain -- Continuous -- Continuous @ 100C -- Single Pulse (tp s)
Adc
PIN ASSIGNMENT
1 2 Gate Drain Source Drain
v10
Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 100 V, VGS = 10 Vdc, IL = 10 A, L = 8 mH, RG = 25 ) Thermal Resistance -- Junction-to-Case -- Junction-to-Ambient(1) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
Watts W/C C mJ
3 4
ORDERING INFORMATION
Device Package D2PAK D2PAK Shipping 50 Units/Rail 800 Tape & Reel
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preferred devices are recommended choices for future use and best overall value.
(c) Semiconductor Components Industries, LLC, 1999
1
October, 1999 - Rev. 0
Publication Order Number: MTB10N60E7/D
MTB10N60E7
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Collector Current (VDS = 600 Vdc, VGS = 0 Vdc) (VDS = 600 Vdc, VGS = 0 Vdc, TJ =125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage ID = 0.25 mA, VDS = VGS Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 5 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 10 Adc) (VGS = 10 Vdc, ID = 5 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge ( (VDS = 400 Vdc, ID = 10 Adc, VGS = 10 Vdc) (VDD = 300 Vdc, ID = 10 Adc, VGS = 10 Vdc Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage(1) (IS = 10 Adc, VGS = 0 Vdc) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125C) Reverse Recovery Time (IS = 10 Adc VGS = 0 Vdc Adc, Vdc, diS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. LD -- -- LS -- 7.5 -- 3.5 4.5 -- -- nH -- -- -- -- -- -- -- -- 20 28 58 36 41 13 6.8 20 40 60 120 70 60 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vd Vd f = 1.0 MHz) Ciss Coss Crss -- -- -- 3300 190 4.0 4620 270 10 pF VGS(th) 2.0 -- RDS(on) VDS(on) -- -- gFS 3.0 -- -- 9.0 9.0 7.9 -- mhos -- 2.8 7.1 0.58 4.0 -- 0.75 Vdc mV/C Ohm Vdc V(BR)DSS 600 -- IDSS -- -- IGSS(f) IGSS(r) -- -- -- -- -- -- 10 100 100 100 nAdc -- 700 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
VSD -- -- trr ta tb QRR -- -- -- -- 0.83 0.7 485 158 327 4.0 1.0 -- -- -- -- --
Vdc
ns
C
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MTB10N60E7
TYPICAL ELECTRICAL CHARACTERISTICS
20 18 ID, DRAIN CURRENT (AMPS) 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 4V 16 4.5 V 6V 8V 5V TJ = 25C VGS = 10 V 5.5 V ID, DRAIN CURRENT (AMPS) 20 17.5 15 12.5 10 7.5 5 - 55C 2.5 0 0 1 2 3 4 5 6 7 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) TJ = 100C 25C VDS 10 V
Figure 1. On-Region Characteristics
R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 ID, DRAIN CURRENT (AMPS) - 55C 25C VGS = 10 V TJ = 100C RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0 2
Figure 2. Transfer Characteristics
TJ = 25C
VGS = 10 V 15 V
4
6
8
10
12
14
16
18
20
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 -50 VGS = 10 V ID = 5 A 10,000
Figure 4. On-Resistance versus Drain Current and Gate Voltage
TJ = 125C 1000 IDSS, LEAKAGE (nA) 100C 100
10
25C VGS = 0 V
1 -25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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MTB10N60E7
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
5000 4500 4000 C, CAPACITANCE (pF) 3500 3000 2500 2000 1500 1000 Crss Coss -5 VGS 0 VDS 5 10 15 20 25 VDS = 0 V VGS = 0 V Ciss TJ = 25C Ciss
500 0 -10
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTB10N60E7
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 11 10 9 8 7 6 5 4 3 2 1 0 0 5 Q3 10 15 20 25 30 VDS VGS Q2 TJ = 25C VDS = 400 V VGS = 10 V ID = 10 A 35 40 600 550 500 450 400 350 300 250 200 150 100 50 0 45 1000 TJ = 25C VDD = 300 V VGS = 10 V ID = 10 A
QT
Q1
100 td(off) tf tr td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable
10 9 I S , SOURCE CURRENT (AMPS) 8 7 6 5 4 3 2 1 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) TJ = 25C VGS = 0 V
circuit parasitic inductances and capacitances acted upon by high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
Figure 10. Diode Forward Voltage versus Current http://onsemi.com
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MTB10N60E7
Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance -- General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For
100 VGS = 20 V SINGLE PULSE TC = 25C 10 1.0 ms 10 ms dc 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 1 10 100 1000 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 10 ms
reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
450 400 350 300 250 200 150 100 50 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 100 ms VDD = 100 V VGS = 10 V IL = 10 A L = 8mH RG = 25W
ID , DRAIN CURRENT (AMPS)
Figure 12. Maximum Rated Forward Biased Safe Operating Area
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
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MTB10N60E7
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.00E-05 1.00E-04 1.00E-03 1.00E-02 t, TIME (s) 1.00E-01 1.00E+00 1.00E+01
Figure 14. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 15. Diode Reverse Recovery Waveform
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MTB10N60E7
PACKAGE DIMENSIONS D2PAK CASE 418B-03 ISSUE C
C E -B-
4
V
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40
A
1 2 3
S
-T-
SEATING PLANE
K G D 3 PL 0.13 (0.005) H
M
J
DIM A B C D E G H J K S V
TB
M
STYLE 2: PIN 1. 2. 3. 4.
E-FET is a trademark of Semiconductor Components Industries, LLC. TMOS is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MTB10N60E7/D

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